Overlapping contacts for semiconductor device

ABSTRACT

A semiconductor device with overlapping contacts is provided. In one aspect, the semiconductor device includes a dielectric layer; a first contact located in the dielectric layer; and a second contact located in the dielectric layer adjacent to the first contact, wherein a portion of the second contact overlaps a top surface of the first contact.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional of U.S. application Ser. No. 13/171,657, filed on Jun. 29, 2011, which is herein incorporated by reference in its entirety.

BACKGROUND

This disclosure relates generally to the field of semiconductor device fabrication, and more particularly to formation of overlapping contacts (or interconnects) for a semiconductor device.

A semiconductor device may include co-planar adjacent contacts that are formed consecutively, during different processing steps. The subsequently formed contacts may need to be electrically connected with one another. FIG. 1 shows a cross-section of an example semiconductor device 100 having an adjacent first contact 102 a and second contact 102 b according to the prior art. First contact 102 a and second contact 102 b are formed during different processing steps, i.e., second contact 102 b is formed after first contact 102 a. First contact 102 a and second contact 102 b are located adjacent to one another in a dielectric layer 101 which may include an oxide or a nitride. Both the first contact 102 a and the second contact 102 b include a liner, in this case including a first liner layer 103 and second liner layer 104, and a contact fill metal 105. Electrical connection between the first contact 102 a and the second contact 102 b only exists at a contact interface 106 at the contact sidewalls. The electrical connection between the first contact 102 a and the second contact 102 b at contact interface 106 may be poor, as the contact interface 106 has a relatively small area, and may be resistive, as the electrical connection occurs across the liner barriers.

BRIEF SUMMARY

In one aspect, a semiconductor device with overlapping contacts includes a dielectric layer; a first contact located in the dielectric layer; and a second contact located in the dielectric layer adjacent to the first contact, wherein a portion of the second contact overlaps a top surface of the first contact.

Additional features are realized through the techniques of the present exemplary embodiment. Other embodiments are described in detail herein and are considered a part of what is claimed. For a better understanding of the features of the exemplary embodiment, refer to the description and to the drawings.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

Referring now to the drawings wherein like elements are numbered alike in the several FIGURES:

FIG. 1 is a cross sectional view of existing first and second contacts formed in a semiconductor device.

FIG. 2 is a flowchart illustrating an embodiment of a method for formation of overlapping first and second contacts.

FIGS. 3 through 5 are a series of cross sectional views illustrating an embodiment of the method of FIG. 3 for formation of overlapping first and second contacts in which:

FIG. 3 illustrates the formation of a first contact.

FIG. 4 illustrates the device of FIG. 3 after etching a recess for a second contact and removing a top portion of the first contact.

FIG. 5 illustrates the device of FIG. 4 after formation of the second contact in the recess and over the top surface of the etched first contact.

FIG. 6 is a flowchart illustrating another embodiment of a method for formation of overlapping first and second contacts.

FIGS. 7 through 10 are a series of cross sectional views illustrating another embodiment of the method of FIG. 6 for formation of overlapping first and second contacts in which:

FIG. 7 illustrates the formation of a first contact.

FIG. 8 illustrates the device of FIG. 7 after etching a recess for a second contact and removing a top portion of the first contact.

FIG. 9 illustrates the device of FIG. 8 after removing an additional top portion of the etched first contact.

FIG. 10 illustrates the device of FIG. 9 after formation of the second contact in the recess and over the top surface of the partially removed first contact.

DETAILED DESCRIPTION

Embodiments of overlapping contacts (or interconnects) for a semiconductor device, and methods for forming overlapping contacts, are provided, with exemplary embodiments being discussed below in detail. The overlapping contacts are formed subsequently, during different processing steps. Physical means may be used to remove a top portion of the first contact before formation of the second contact. A portion of the second contact may then be formed on a top surface of the partially removed first contact such that the second contact overlaps the first contact. This results in a relatively large contact interface are between the first and second contacts, and gives a correspondingly improved electrical connection between the first and second contacts. Partial removal of the first contact may be accomplished by etching, or by etching in conjunction with an agitated physical clean in various embodiments. Overlapping contacts may be used in many types of electrical devices, including but not limited to static random access memory (SRAM), and for connections including but not limited to logical cross-couples or power rails.

Turning to FIG. 2, a flowchart of an embodiment of a method 200 for formation of overlapping first and second contacts is shown. In block 201, a first contact, as shown in FIG. 3, is formed. The first contact 302 is formed in a dielectric layer 301 a-b. The first contact 302 includes a liner, including outer liner layer 303 and inner liner layer 304, and a contact fill metal 305. Contact fill metal 305 may be, for example, tungsten. Outer liner layer 303 may be, for example, titanium nitride, and the inner liner layer 304 may be, for example, titanium. The dielectric layer 301 a-b may include, for example, a nitride or an oxide. In the exemplary embodiment shown in FIG. 3, the dielectric layer includes top dielectric layer 301 a and bottom dielectric layer 301 b comprising different dielectric materials; in other embodiments, the dielectric layer may include a single dielectric material.

In block 202 of FIG. 2, a recess is formed in the dielectric layer, and a top portion of first contact 302 is removed. Recess formation and partial removal (or pullback) of first contact 302 may be performed by etching. As shown in FIG. 4, the etch process performed in block 202 of FIG. 2 forms a recess 402 in the dielectric layer 301 a-b, and also removes a top portion of the first contact 302, resulting in an etched first contact 401. In an exemplary embodiment, the etch process may include reactive ion etching (RIE) or wet etching. In embodiments in which the dielectric layer 301 a-b includes top dielectric layer 301 a and bottom dielectric layer 301 b comprising different dielectric materials, the recess 402 may be formed in the top dielectric layer 301 a, such that the interface between the top dielectric layer 301 a and bottom dielectric layer 301 b serves as an etch stop during the etch that forms the recess 402, thereby determining the depth of the recess 402 in dielectric layer 301 a-b. In such an embodiment, the bottom of recess 402 is therefore located at the top of the bottom dielectric layer 301 b, as shown in FIG. 4.

Lastly, in block 203 of FIG. 2, a second contact 501 is formed adjacent to and on a top surface of the etched first contact 401, as shown in FIG. 5. Second contact 501 may comprise outer and inner liner layers and a contact fill metal such as are described above with respect to first contact 302 in the section discussing block 201. At least a portion of the second contact 501 is located directly on top of the etched first contact 401, such that contacts 401 and 501 overlap, and the outer liner layer of second contact 501 is in contact with the fill metal on the top surface of the first contact 401 along contact interface 502. Contacts 401 and 501 are electrically connected along a contact interface 502 at the top surface of first contact 401, which provides a relatively large contact interface area, in turn allowing a good electrical connection between contacts 401 and 501. After the formation of second contact 501, the device 500 may be polished using, for example, chemical mechanical polishing (CMP).

In a second embodiment of a method for formation of overlapping first and second contacts, which is illustrated in FIG. 6, partial removal of the first contact is a two-step process, including an additional partial removal step that is performed in after the etching is completed and the recess is formed. The recess may be formed such that a top portion of the partially removed first contact is completely surrounded by the recess, i.e., is not anchored in the dielectric. The additional partial removal step includes an aggressive agitated physical clean such as megasonics to physically knock down and remove a top portion of the partially removed first contact that is not anchored in the dielectric. Turning to FIG. 6, in block 601, a first contact, as shown in FIG. 7, is formed. The first contact 702 is formed in a dielectric layer 701. The first contact 702 includes contact fill metal 705 and a liner including outer liner layer 703 and inner liner layer 704. Contact fill metal 705 may be tungsten, for example. Outer liner layer 303 may be titanium nitride, for example, and inner liner layer 704 may be titanium, for example. The dielectric layer 701 may be a nitride or an oxide, and may include top and bottom dielectric layers comprising different dielectric materials in some embodiments (as described above with respect to dielectric layer 301 a-b), or a single dielectric material in other embodiments.

In block 602, a recess is etched in the dielectric, and a top portion of the first contact is removed during the etch. As shown in FIG. 8, the etch performed in block 602 of FIG. 6 forms a recess 802 in the dielectric 701, and also removes a top portion of first contact 702, resulting in etched first contact 801. The etch may include RIE or wet etching. Recess 802 is formed all around the etched first contact 801, such that an upper portion of the etched first contact 801 is not anchored in the dielectric 701.

Then, in block 603 of FIG. 6, an additional top portion of etched first contact 801 is removed, resulting in partially removed first contact 901 shown in FIG. 9. Removal of the additional top portion of the contact may allow for a longer contact interface between the first contact and the second contact (discussed below with respect to block 604 of FIG. 6). Any appropriate amount of the etched first contact 801 may be removed during the additional contact removal step of block 603 of FIG. 6; some or all of the top portion of the first contact 801 that is not anchored in the dielectric 701 may be removed. In some embodiments, the top of partially removed first contact 901 may be approximately even with the surface of dielectric 701 after the additional partial contact removal step of block 603 of FIG. 6. The additional partial contact removal may include an aggressive agitated physical clean of the top surface of the etched first contact 801. The agitated physical clean may include megasonics, ultrasonics, cryogenic aerosol, or a pressurized and atomized liquid in various embodiments. In the ultrasonics and megasonics techniques, energy is applied to a liquid solution that is placed on the surface being cleaned, causing microbubbles to form in the liquid solution (referred to as a cavitation event). When the microbubbles collapse, the energy from the collapse is transferred to the surface, resulting in the removal of surface particles or patterning of damage-sensitive portions of the surface. Cryogenic aerosols are another physical method of creating intentional pattern damage on a surface. In the cryogenic aerosol technique, a surface is bombarded with an aerosol mixture, which may include argon (Ar), nitritrogen gas (N₂) and/or carbon dioxide (CO₂) mixtures. The aerosol mixture vaporizes when it hits the surface. The combination of physical bombardment by the aerosol mixture coupled with the sublimation phase change of the aerosol mixture that occurs on the surface removes particles from or cause desired pattern damage to the surface. Atomized liquid droplets may also be used to cause pattern damage to a surface, with appropriate droplet size and pressure of the atomized liquid. Any of these approaches may be used to physically knock down and remove the upper portion of the etched first contact 801 that is not anchored in the dielectric 701.

Lastly, in block 604 of FIG. 6, a second contact 1001 is formed over the top surface of the partially removed first contact 901, as shown in FIG. 10. Second contact 1001 may comprise outer and inner liner layers and a contact fill metal such as are described above with respect to first contact 702 in the section discussing block 601. Second contact 1001 completely covers partially removed first contact 901, such that contacts 901 and 1001 overlap, and the outer liner layer of second contact 1001 is in contact with the fill metal on the top surface of the first contact 901 along contact interface 1002. Contacts 901 and 1001 are electrically connected along contact interface 1002 at the top of first contact 901, which provides a relatively large contact surface area, allowing a good electrical connection between contacts 901 and 1001. After formation of second contact 1001, the device 1000 may be polished using, for example, CMP.

The technical effects and benefits of exemplary embodiments include improvement of an electrical connection between two contacts formed during different processing steps by increasing the area of the interface between the two contacts.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an”, and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated. 

1. A semiconductor device with overlapping contacts comprises: a dielectric layer; a first contact located in the dielectric layer; and a second contact located in the dielectric layer adjacent to the first contact, wherein a portion of the second contact overlaps a top surface of the first contact.
 2. The semiconductor device of claim 1, wherein the second contact completely covers the top surface of the first contact.
 3. The semiconductor device of claim 1, wherein the first contact comprises a liner, the liner comprising a first outer liner layer located adjacent to the dielectric layer, a first inner liner layer located over the first outer liner layer, and a first contact fill metal located over the first inner liner layer; and wherein the second contact comprises a second outer liner layer, wherein a first portion of the second outer liner layer is located adjacent to the dielectric layer, and a second portion of the second outer liner layer is located adjacent to the first contact fill metal on the top surface of the first contact, a second inner liner layer located over the second outer liner layer, and a second contact fill metal located over the second inner liner layer.
 4. The semiconductor device of claim 3, wherein the first and second outer liner layers comprise titanium, the first and second inner liner layers comprises titanium nitride, and the first and second contact fill metal comprises tungsten.
 5. The semiconductor device of claim 1, wherein the dielectric layer comprises one of an oxide and a nitride.
 6. The semiconductor device of claim 1, wherein the dielectric layer comprises a top dielectric layer and a bottom dielectric layer, the top dielectric layer and the bottom dielectric layer comprising different dielectric materials.
 7. The semiconductor device of claim 6, wherein the second contact is located in the top dielectric layer and on top of the bottom dielectric layer. 